A persistent trend is towards smaller and smaller integrated circuits. One aspect of attempts to reduce chip size is the reduction in line size for metal interconnects. However, in the current processes, a reduction in line size generally results in a reduction in grain size. In particular, the current design for interconnects in computer chips consists of etching a trench into oxide and filling the trench with a metal, typically copper. This is commonly referred to as damascene processing. For example, dual damascene back-end-of-the-line (BEOL) processing is a leading technique for forming line-via interconnect structures. Because these trenches are shrinking, the grains within the copper are decreasing as well. As a consequence of reduced grain size, there is a corresponding increase in resistance/resistivity in the line due to grain boundary scattering. Surface scattering also increases as the line size is reduced. These factors further contribute to increased resistance/resistivity. However, grain boundary size remains the dominating aspect in increased resistance/resistivity that comes with decreasing line size in the conventional process.